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vishay siliconix dg401b, dg403b, dg405b document number: 73069 s11-0179-rev. b, 07-feb-11 www.vishay.com 1 low-power, high-speed cmos analog switches features ? 44 v supply max rating ? 15 v analog signal range ? on-resistance - r ds(on) : 23 ? ? low leakage - i d(on) : 40 pa ? fast switching - t on : 100 ns ? upgrade to dg401b, dg403b, dg405b ? ttl, cmos compatible ? single supply capability benefits ? wide dynamic range ? break-before-make switching action (dg403b only) ? simple interfacing applications ? audio and video switching ? sample-and-hold circuits ? test equipment ? pbx, pabx description the dg401b, dg403b, dg405b monolithic analog switches are replacements for the popular dg401/403/405 analog switches and provide improved performance, combining high speed (t on : 100 ns, typ) with low power consumption make the dg401b series ideal for portable and battery powered applications. built on the vishay siliconix proprietary high-voltage silicon- gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the spdt configurations. each switch conducts equally well in both directions when on, and blocks up to 30 v peak-to-peak when off. on-resistance is very flat over the full 15 v analog range. the dg401b has two independent spst switches. the dg403b has four spst switc hes in no/nc combinations. the dg405b has four switch es in two spst pairs (see functional block diagrams and pin configurations on pages 1 and 2.) the dg401b, dg403b, dg405b is available in both 16-pin plastic dip and 16-pin soic packages. as a committed partner to the community and the environment, vishay siliconix manufactures this product with the lead (pb)-free device terminations. for analog switching products manufactured with 100 % matte tin device terminations, the lead (pb)-free ?-e3? suffix is being used as a designator. functional block diagram and pin configuration two spst switches per package logic ?0? ?? 0.8 v logic ?1? ?? 2.4 v dg401b nc gnd nc nc nc v+ nc in 2 d 2 s 2 d 1 s 1 nc dual-in-line and soic in 1 nc v- 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view truth table logic switch 0 off 1on
www.vishay.com 2 document number: 73069 s11-0179-rev. b, 07-feb-11 vishay siliconix dg401b, dg403b, dg405b functional block diagram and pin configuration four spst switches in two pairs per package logic ?0? ?? 0.8 v logic ?1? ?? 2.4 v four spst switches in two pairs per package logic ?0? ?? 0.8 v logic ?1? ?? 2.4 v dg403b d 1 s 1 nc dual-in-line and soic in 1 d 3 v- s 3 gnd s 4 nc d 4 v+ nc in 2 d 2 s 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view truth table logic sw 1 , sw 2 sw 3 , sw 4 0 off on 1onoff dg405b d 1 s 1 nc dual-in-line and soic in 1 d 3 v- s 3 gnd s 4 nc d 4 v+ nc in 2 d 2 s 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view truth table logic switch 0 off 1on ordering information standard commercial part number lead (pb)-free commercial part number package temperature range dg401bdj dg401bdj-e3 16-pin plastic dip - 40 to 85 c dg403bdj dg403bdj-e3 dg405bdj dg405bdj-e3 dg401bdy dg401bdy-e3 16-pin narrow soic dg403bdy dg403bdy-e3 dg405bdy dg405bdy-e3 dg401bdy-t1 dg401bdy-t1-e3 16-pin narrow soic with tape and reel dg403bdy-t1 DG403BDY-T1-E3 dg405bdy-t1 dg405bdy-t1-e3
document number: 73069 s11-0179-rev. b, 07-feb-11 www.vishay.com 3 vishay siliconix dg401b, dg403b, dg405b notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes. limit forward di ode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/c above 75 c. d. derate 7.6 mw/c above 75 c. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. absolute maximum ratings parameter symbol limit unit v+ to v- 44 v gnd to v- 25 digital inputs a , v s , v d (v-) - 0.3 v to (v+) + 0.3 v or 30 ma, whichever occurs first current (any terminal) continuous 30 ma current, s or d (pulsed 1 ms 10 % duty) 100 storage temperature (dj, dy suffix) - 65 to 125 c power dissipation (package) b 16-pin plastic dip c 450 mw 16-pin soic d 600 specifications a parameter symbol test conditions unless specified v+ = 15 v, v- = - 15 v v in = 2.4 v, 0.8 v f temp. b limits - 40 c to 85 c unit min. d typ. c max. d analog switch analog signal range e v analog full -15 15 v drain-source on-resistance r ds(on) i s = - 10 ma, v d = 10 v v+ = 13.5 v, v- = - 13.5 v room full 23 45 55 ? ? drain-source on-resistance ? r ds(on) i s = - 10 ma, v d = 5 v, 0 v v+ = 16.5 v, v- = - 16.5 v room full 0.72 3 5 switch off leakage current i s(off) v+ = 16.5, v- = - 16.5 v v d = 15.5 v, v s = 15.5 v room hot - 0.5 - 5 - 0.01 0.5 5 na i d(off) room hot - 0.5 - 5 - 0.01 0.5 5 channel on leakage current i d(on) v+ = 16.5 v, v- = - 16.5 v v s = v d = 15.5 v room hot - 1 - 10 - 0.04 1 10 digital control input current v in low i il v in under test = 0.8 v, all other = 2.4 v full - 1 0.005 1 a input current v in high i ih v in under test = 2.4 v, all other = 0.8 v full - 1 0.005 1 dynamic characteristics tu r n - o n t i m e t on r l = 300 ? , c l = 35 pf see figure 2 room 100 150 ns turn-off time t off room 60 100 break-before-make time delay (dg403b) t d r l = 300 ? , c l = 35 pf room 5 12 charge injection q c l = 10 000 pf, v gen = 0 v, r gen = 0 ? room 60 pc off isolation reject ratio oirr r l = 100 ? , c l = 5 pf, f =1 mhz room - 81.7 db channel-to-channel crosstalk x ta l k room - 94.8 source off capacitance c s(off) f = 1 mhz, v s = 0 v room 12 pf drain off capacitance c d(off) room 12 channel on capacitance c d , c s(on) room 39
www.vishay.com 4 document number: 73069 s11-0179-rev. b, 07-feb-11 vishay siliconix dg401b, dg403b, dg405b notes: a. refer to process option flowchart. b. room = 25 c, full = as determin ed by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. typical characteristics (25 c, unless otherwise noted) specifications a parameter symbol test conditions unless specified v+ = 15 v, v- = - 15 v v in = 2.4 v, 0.8 v f temp. b limits - 40 c to 85 c unit min. d typ. c max. d power supplies positive supply current i+ v+ = 16.5 v, v- = - 16.5 v v in = 0 or 5 v room full 0.250 0.5 1 ma negative supply current i- room full - 0.5 - 1 0.25 ground current i gnd room full - 0.5 - 1 0.25 supply current vs. temperature - 55 - 25 5 35 65 95 125 temperature (c) i cc - supply current (pa) v+ = 15 v v- = - 15 v 1 10 100 1000 100 000 10 000 i+ i- supply current vs. switching frequency 0 10 20 30 40 50 60 0 2000 4000 6000 8000 10000 12000 frequency (khz) supply current (ma)
document number: 73069 s11-0179-rev. b, 07-feb-11 www.vishay.com 5 vishay siliconix dg401b, dg403b, dg405b typical characteristics (25 c, unless otherwise noted) r on vs. analog voltage and supply voltage r on vs. analog voltage and temperature leakage current vs. temperature 10 15 20 25 30 35 40 45 50 55 60 - 25 - 20 - 15 - 10 - 5 0 5 10 15 20 25 v d - analog voltage (v) r on - on-resistance ( ) v cc = 6 v v cc = 10 v v cc = 12 v v cc = 15 v v cc = 20 v v cc = 22 v 10 15 20 25 30 35 40 45 50 55 60 - 15 - 10 - 5 5 01015 v d - analog voltage (v) r on - on-resistance ( ) v cc = 15 v i s = 10 ma 125 c 85 c 25 c 0 c - 40 c - 55 c - 55 - 25 5 35 65 95 125 temperature (c) leakage current (pa) 1 10 100 1000 10 000 i s(off) i d(on) i d(off) r on vs. analog voltage and single supply voltage leakage current vs. analog voltage switching time vs. supply voltage 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 v d - analog voltage (v) r on - on-resistance ( ) v cc = 7.5 v v cc = 10 v v cc = 12 v v cc = 15 v v cc = 20 v v cc = 22 v - 100 - 80 - 60 - 40 - 20 0 20 40 60 80 100 - 15 - 5 1 55 v d - analog voltage (v) leakage current (pa) v+ = 15 v v- = - 15 v for i d(off) , v s = 0 v for i s(off) , v d = 0 v i d(on) i d(off) i s(off) 0 25 50 75 100 125 150 su pp l y volta g e ( v ) switching time (ns) t (on) , v s = + 5 v t (on) , v s = - 5 v t (off) , v s = - 5 v t (off) , v s = + 5 v 0 5 10 15 20 25
www.vishay.com 6 document number: 73069 s11-0179-rev. b, 07-feb-11 vishay siliconix dg401b, dg403b, dg405b typical characteristics (25 c, unless otherwise noted) schematic diagram (typical channel) switching time vs. single supply voltage input switching threshold vs. supply voltage 0 25 50 75 100 125 150 175 200 225 250 0 5 10 15 20 25 supply voltage (v) switching time (ns) t (on) , v s = + 5 v t (off) , v s = + 5 v 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 5 1015202530 v th - input threshold voltage (v) supply voltage (v) switching time vs. temperature insertion loss, off -isolation crosstalk vs. frequency 20 30 40 50 60 70 80 - 55 - 25 5 35 65 95 125 switching time (ns) temperature (c) t (on) , v s = + 10 v t (on) , v s = - 10 v t (off) , v s = + 10 v t (off) , v s = - 10 v v+ = 15 v v- = - 15 v talk 0.01 130 0.1 30 -10 70 1000 frequency (mhz) 90 1 loss, oirr, x (db) 110 10 100 10 cross talk 50 insertion loss off isolation figure 1. level shift/ drive v in s v+ gnd v- d v- v+
document number: 73069 s11-0179-rev. b, 07-feb-11 www.vishay.com 7 vishay siliconix dg401b, dg403b, dg405b test circuits v o is the steady state output with the switch on. feedthrough via switch capacitance may resu lt in spikes at the leading and trailing edge of the output waveform. figure 2. switching time 0 v logic input switch input* switch output 3 v 0 v switch input* v s t r < 20 ns t f < 20 ns 90 % - v s t off t on v o 90 % v o * v s = 10 v for t on , v s = - 10 v for t off note: logic input waveform is inverted for switches that have the opposite logic sense control c l (includes fixture and stray capacitance) v+ in r l r l + r ds(on) v o = v s s d - 15 v v o gnd 10 v c l 35 pf v- r l 1 k + 15 v 50 % figure 3. break-before-make 0 v logic input switch switch output 3 v 50 % 0 v output 0 v 90 % v o2 v o1 90 % v s1 v s2 t d t d v o2 c l (includes fixture and stray capacitance) v+ r l1 s 2 c l1 v- s 1 v s2 in d 2 v s1 r l2 d 1 v o1 c l2 - 15 v gnd + 15 v figure 4. charge injection off on on in v o v o q = v o x c l c l 10 nf d r g v o v+ s v- 3 v in v g - 15 v gnd + 15 v
www.vishay.com 8 document number: 73069 s11-0179-rev. b, 07-feb-11 vishay siliconix dg401b, dg403b, dg405b test circuits figure 5. off isolation figure 7. crosstalk r l 100 d 0 v, 2.4 v v+ r g = 50 - 15 v gnd v- c v s off isolation = 20 log v s v o in v o + 15 v s c c = rf bypass r g = 50 in 0.8 v v+ v- x talk isolation = 20 log v s v o gnd s 2 v s v o s 1 r l d c = rf b yp ass 50 + 15 v - 15 v c c figure 6. insertion loss figure 8. capacitances r l 100 s v s v o 0 v, 2.4 v in d r g = 50 - 15 v gnd v- c + 15 v v+ c c = rf bypass d f = 1 mhz in s v+ - 15 v gnd v- c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent + 15 v c
document number: 73069 s11-0179-rev. b, 07-feb-11 www.vishay.com 9 vishay siliconix dg401b, dg403b, dg405b applications dual slope integrators the dg403b is well suited to configure a selectable slope integrator. one control signal selects the timing capacitor c 1 or c 2 . another one selects e in or discharges the capacitor in preparation for the next integration cycle. band-pass switched capacitor filter single-pole double-throw switches are a common element for switched capacitor netwo rks and filters. the fast switching times and low leak age of the dg403b allow for higher clock rates and consequent ly higher filter operating frequencies. figure 9. stereo source selector dg403b right right left left channel select source 1 source 2 ttl left right - 15 v + 15 v gnd v- v+ s 1 in 2 s 3 s 2 s 4 d 1 d 3 d 2 d 4 in 1 figure 10. dual slope integrator dg403b integrate/ reset slope select ttl + - - 15 v + 15 v gnd v- v+ s 1 in 2 s 3 s 2 s 4 d 1 d 3 d 2 d 4 in 1 c 1 c 2 e out e in figure 11. band-pass switched capacitor filter - 15 v + 15 v gnd v- v+ clock + - e out e in dg403b s 1 in 2 s 3 s 2 s 4 d 1 d 3 d 2 d 4 in 1
www.vishay.com 10 document number: 73069 s11-0179-rev. b, 07-feb-11 vishay siliconix dg401b, dg403b, dg405b applications peak detector a 3 acting as a comparator provides the logic drive for operating sw 1 . the output of a 2 is fed back to a 3 and compared to the analog input ein. if e in > e out the output of a 3 is high keeping sw 1 closed. this allows c 1 to charge up to the analog input voltage. when e in goes below e out a 3 goes negative, turning sw 1 off. the system will therefore store the most positive analog input experienced. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73069 . figure 12. positive peak detector a 2 + ? e out + ? a 3 + ? a 1 e in reset sw 1 sw 2 r 1 c 1 dg401b
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 12345678 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71261 06-jul-01 www.vishay.com 1

dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 18.93 21.33 0.745 0.840 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.38 1.52 .015 0.060 ecn: s-03946?rev. d, 09-jul-01 dwg: 5482
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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